Abstract

Based on the 0.5 μm GaAs enhancement/depletion (E/D) Pseudomorphic High Electron Mobility Transistor (pHEMT) process, a 7.5–9 GHz two-channel amplitude phase control multi-function chip (MFC) was developed successfully. The chip was integrated with a 6-bit digital phase shifter, a 6-bit digital attenuator, and a single pole single throw (SPST) switch in each channel. A design for the absorptive SPST switch is deployed to optimize the return loss and control channel array calibration. In the 8 dB and 16 dB attenuation bit, a switched-path-type topology is employed in order to obtain a good flatness of attenuation characteristic and achieve low additive phase shift. A 27-bit serial-to-parallel converter (SPC) was introduced to decrease the control lines and pads of the chip, and the power consumption was less than 70 mW. The measurement result shows that the insertion loss is less than −13 dB and the return loss is better than −19 dB. In both channels, the 64-state root mean square (RMS) errors of the phase shifter is less than 2° and the RMS parasitic amplitude error is less than 0.2 dB. The RMS attenuation error is less than 0.45 dB and the RMS parasitic phase error is less than 2.4°. The size of the chip is 3.5 mm × 4.5 mm.

Highlights

  • Phased array technologies have been widely applied to satellite communications and defense systems to implement high-performance radar systems [1]

  • Packing the multi-function chip (MFC) for compact and low cost T/R modules has already been realized in a phased array system [3]

  • 7 results shows the27photograph of the multi-function chip whichThe is fabricated by (DCFL)

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Summary

Introduction

Phased array technologies have been widely applied to satellite communications and defense systems to implement high-performance radar systems [1]. Phased array radar systems consist of thousands of T/R modules which increase the systems’ complexity and cost. By integrating several functions such as phase and gain control, driver amplifiers, and switches on a single multi-function chip [2], the sharp problem can be solved. Packing the multi-function chip (MFC) for compact and low cost T/R modules has already been realized in a phased array system [3]. Several GaAs multi-function chips have been presented, but higher integration implies a large number of control lines and pads to the chips [5,6,7]. By combination of serial-to-parallel converter on-chip, the number of control lines and pads can be substantially reduced [8,9]. With high performance and high integration, the MFC chips must be promising

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