A G-band SPST switch with 2.4-dB insertion loss and minimum 28.5-dB isolation using grounded co-planar waveguide folded coupled line topology in 65-nm CMOS technology

Abstract

A G-Band single pole single throw (SPST) switch for low insertion loss and high isolation is proposed and fabricated using 65-nm CMOS technology. A grounded co-planar wave guide (GCPW) folded coupled line topology is developed to improve the switch isolation and lower its insertion loss simultaneously. Based on this topology, this switch achieves minimum 2.4-dB insertion loss (IL) in G-Band with minimum 28.5-dB isolation (ISO). This switch consumes only 0.0067 mm2 chip area. To the authors' knowledge, this CMOS SPST switch achieves the best performance among the published switches in bulk CMOS processes at this frequency.