A 72 k CMOS track–free gate array with embedded 1 Mbit DRAM

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AbstractA 72 k CMOS track‐free gate array with embedded 1‐Mbit DRAM has been fabricated using 1.0 μm HC2MOS twin‐well process technology. This is considered to be one of the solutions for the applications of audio/visual signal processing that require high‐density memories of megabit class on a chip.Based on the evaluation and discussion of the fabricated test devices, this paper reports the possibility of logic LSI's with embedded DRAM that has been assumed difficult. As for the design of the DRAM part, several kinds of optimized design were introduced considering the process compatibility and noise immunity against the gate array. For example, the substrate bias‐free design, the virtual/pseudo SRAM mode and the cell within the isolated P well were considered.The high noise immunity in the real usage is confirmed by the evaluation utilizing the emulated noise generator circuit fabricated by the evaluation utilizing the emulated noise generator circuit fabricated in the gate array part. The delay time in the gate array is 0.4 ns and the worst case access time in the DRAM is 60 ns.