A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder

Abstract

A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analog-to-digital converter (ADC) and forward error correction (FEC) decoder is presented. The chip accepts an analog 2 V/sub pp/ differential QAM signal centered at an intermediate frequency. The integrated 10 b ADC digitizes the IF signal, and all subsequent signal processing, including demodulation, timing/carrier recovers, adaptive equalization, and FEC, is performed digitally. The receiver IC is capable of receiving 4, 16, 32, 63, 128, 256, and 1024-QAM modulation formats. The 0.5-/spl mu/m triple level metal N-well CMOS chip has a complexity of 650 k transistors with a core area of 1.9/spl times/4.9 mm/sup 2/. Power dissipation is 1.8 W at 7 MBaud and 5 V.