A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Abstract

A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feed-forward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.