Abstract
In this paper, we propose a 6-bit, 1GS/s digital-to-analog converter (DAC) for Automotive Ethernet PHY. In our design, we first present an optimized unit current source by introducing a pair of small current branches. This effectively enhances the DAC’s SFDR performance at high frequency. Meanwhile, we proposed a novel latch with a high crosspoint to further improves the DAC’s dynamic performance. To validate the performance of the proposed DAC, a prototype has been fabricated in the standard 0.13um CMOS process. The core area is about 350 µm×360 µm. The proposed DAC achieves an SFDR of 46.60dB as the input signal frequency and sampling frequency are respectively 30MHz and 1GHz. The measured DNL/INL is 0.02/0.03LSB. The experimental results indicate that the proposed DAC is suitable for Automotive Ethernet PHY applications.
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