Effective Elimination of Analog Impairments Error in Parallel Interleaving Sigma Delta A/D Converters: A Recent Study

Abstract

Oversampling sigma delta modulators that produce one bit samples of input signals can be utilized to make AD converters that can produce multi bit samples with high resolution but low sampling frequency, or poor resolution samples with high sampling frequency. Using numerous converters running in parallel in a time interleaved manner is one approach of overcoming this limitation. The resolution of the converter's digital output can be greatly increased in this manner, reducing the quantising error value. However, parallel converters' analogue flaws induce modulation of the output samples, which can significantly deteriorate the converter's capabilities. Many articles detailing different architectures of \(\Sigma-\Delta\) AD converters limit their analysis to the frequency domain, ignoring the fact that \(\Sigma-\Delta\) modulators are synchronous voltage to frequency converters. This paper shows how, by understanding the time domain properties of \(\Sigma-\Delta\) modulators, the problem of analogue converter impairments can be overcome, resulting in a better design of high resolution \(\Sigma-\Delta\) AD converters.