Abstract
This paper presents a 375-GB/s/mm power-efficient memory interface that consists of the PAM-4 transceivers with a per-pin training system for the next-generation HBM controllers. The self-training system executes foreground driver calibration, 2-D sampling point optimization, FFE coefficient adaptation, and sampler offset calibration. Using DC-levels and SBR patterns, the entire training sequence for 8 DQ transceivers and 2 DQS transceivers takes less than 1-ms. In addition, a charge-recycling sampler that saves 44.5% of power consumption compared to the strongARM latch sampler is proposed. The proposed memory interface fabricated in a 40-nm CMOS process shows a power efficiency of 0.41-pJ/b and a power efficiency per channel length of 68.7-fJ/b/mm, significantly higher than the standard state-of-the-art memory interfaces.
Published Version
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