A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

Abstract

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 $\times $ improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.