A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS

Abstract

A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is presented. The receiver equalization relies on a flexible continuous-time linear equalizer (CTLE), providing a very accurate channel inversion through a transfer function that can be optimally adapted at low frequency, mid-frequency, and high frequency independently. The CTLE meets the performance requirements of CEI-56G-VSR without requiring the decision feedback equalizer (DFE) implementation. As a result, timing constraints for comparators in data and edge sampling paths may be relaxed by using track-and-hold (T&H) stages, saving power consumption. At the maximum speed, the receiver draws 180 mA from 1-V supply, corresponding to 2.8 mW/Gb/s only. The transmitter embeds a flexible feed-forward equalizer (FFE) which can be reconfigured to comply with legacy standards. A comparison between current-mode (CM) and voltage-mode (VM) TX drivers is proposed, proving through experiments that the latter yields larger PAM-4 eye openings, thanks to the intrinsically higher speed. The full transceiver (TX, RX, and clock generation) operates from 16 to 64 Gb/s in PAM-4 and 8 to 32 Gb/s in non-return-to-zero (NRZ), and supports 2× and 4× oversampling to reduce data rate down to 2 Gb/s. A TX-to-RX link at 64 Gb/s, across a 16.8-dB-loss channel, reaches 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> minimum bit-error rate (BER) and 0.19-UI horizontal eye opening at BER = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> , with 5.02 mW/Gb/s power dissipation.