A 60-GHz 32-Way Hybrid Power Combination Power Amplifier in 55-nm Bulk CMOS

Abstract

This article presents a high output power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band power amplifier (PA) with 32-way power combining in 55-nm bulk CMOS. A new hybrid power combiner (HPC) is proposed and utilized to output combination network of PA. Incorporating the impedance matching requirements, a general model and analysis equations are given, from which it can be seen that HPC increases the design flexibility and reduces the difficulty of multiway power combiner using a single approach, while simultaneously considering asymmetry caused by parasitic capacitance and chip layout distribution. The adoption of HPC also takes into account the inconsistencies between the internal and external channels of the chip due to thermal distribution, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R$ </tex-math></inline-formula> drop, and so on. To the best of our knowledge, this is the first time that the challenges and considerations of high-power PA design in silicon-based process are comprehensively presented, and two test printed circuit boards (PCBs) are used to compare and improve the thermal problem of high-power PAs during testing. The PA achieves a small-signal gain of 21.9 dB at 60 GHz and a saturated output power of 24.42–25.06 dBm at 57–62 GHz with a maximum output 1-dB compression point of 21.87 dBm and a peak power-added efficiency (PAE) of 11%. The core area is 1.77 mm2.