A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS

Abstract

The rapid scaling of CMOS technology in the last decade has enabled the design of high speed and efficient digital CMOS circuits. However, the design of RF and mm-wave systems has become more challenging due to inaccuracies in modeling and increased losses in the active and passive devices. This paper presents the design of a 60 GHz linear wideband power amplifier (PA) in deeply scaled 28 nm CMOS technology. The PA utilizes cascode drain-source neutralization to improve stability and low-k transformer techniques to achieve high bandwidth. Using transmission line power combining, the PA delivers a saturated output power of 16.5 dBm with a peak power added efficiency (PAE) of 12.6%. The three stage PA achieves an overall bandwidth of 11 GHz with a peak gain of 24.4 dB.