A 6 to 12 GHz wideband analog voltage‐controlled phase shifter with IL compensation architecture

Abstract

AbstractThis article describes a 6–12 GHz voltage‐controlled analog phase shifter (APS) with small gain variation range and low phase error. An insertion loss compensation architecture for reducing the gain error of the whole circuit is proposed to compress the gain variation range. The combination of a quadrature signal generator and an analog adder is used to save area and power. Implemented in 0.18 μm SiGe BiCMOS technology, the proposed APS achieves the coverage of 180° continuous phase variation with the gate voltages VI and VQ monotonously changing from 1.6 to 2.4 V. And the core size of the chip excluding the pads is 0.215 mm2. The measured RMS phase and gain errors are below 3.94° and 2.67 dB in the design frequency range for all effective phase state, respectively. The power consumption of the phase shifter is 89.1 mW upon 3.3 V supply voltage.