A 7.2‐mW 0.5–7.5‐GHz ultra‐wideband low‐noise amplifier with 4 dB noise figure and 20 dB gain using 40 nm CMOS technology

Abstract

AbstractThe technology, design procedure, and measurements of an ultra‐wideband (UWB) push–pull high‐performance complementary metal‐oxide semiconductor (CMOS) low‐noise amplifier (LNA) are presented in this letter. While the push–pull LNA exhibits commendable direct current (DC) power consumption, its operational bandwidth is often limited by the inherent parasitic parameters of the transistors. To exploit the parasitic parameters of the transistors, a multipole‐tuning circuit that utilizes pole‐tuning inductors and parasitic capacitors of the MOS to extend the operational bandwidth is proposed. A UWB LNA is implemented using a commercial 40‐nm CMOS process, and the measurement results demonstrate a peak gain of 20.2 dB, an exceptionally wide bandwidth of 0.5–7.5 GHz, a noise figure of 4 dB, and an output power of 3.5 dBm at OP1 dB with 7.2 mW DC power consumption. The chip area of the LNA is a compact 0.26 mm2. Experimental results closely align with simulations, confirming the validity of the concept and showcasing its competitive performance.