Abstract

This paper introduces a current reference based on Δ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>GS</sub></i> generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6V with a line sensitivity equal to 1.2 %/V in the range [0.8-1.8]V and a temperature coefficient equal to 6.3 ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.

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