A 57–78 GHz Frequency Tripler MMIC in 65-nm CMOS

Abstract

In this letter, we present a MMIC frequency tripler using 65-nm CMOS technology. The tripler consists of a buffer stage that overdrives tripler devices into non-linear region, maximizing the third harmonic generation. Adopting differential architecture and transformers impedance matching, the tripler needs no explicit passive filter to enhance harmonic rejections. The tripler shows peak conversion gain of 1.3 dB, saturated output power of −2 dBm with −5 dBm input power. The 3-dB bandwidth spans 57–78 GHz with 60 mW dc consumption.