A 56 Gb/s Half-Rate PAM4 SerDes Receiver with LC-VCO Based CDR in 40-nm CMOS Technology

Abstract

This paper presents a compact 56 Gb/s 4-level pulse amplitude modulation (PAM4) SerDes receiver, which employs a half rate architecture. By employing a LC voltage control oscillator (LC-VCO) based clock and data recovery (CDR), the jitter of the receiver is greatly reduced, and the complexity and noise of the system are also decreased. The CDR is implemented in a type-II bang-bang phase-locked loop (BBPLL) topology. To reduce the locking time and improve the stability of CDR, all of the PAM4 signal transitions with the central crossover point chosen by a waveform filter are utilized to extract the phase error. The receiver is designed in a 40-nm CMOS technology and supplied with 1.1 V and the core circuit occupy an area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The simulation results show that the proposed PAM4 receiver can work at 56 Gbit/s with 172 mW consumption.