A 5.5 GHz low-power PLL using 0.18-µm CMOS technology

Abstract

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-µm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are −85 dBc/Hz and −116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.