Abstract
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> low-phase-noise inverse-class-F (class-F<sup>−1</sup>) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2<sup>nd</sup>-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868fs<sub>rms</sub> jitter in a fractional-N channel when consuming only 529<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>, corresponding to a figure-of-merit (FoM) of −244dB.
Highlights
R ECENT years have witnessed the rapid development of internet-of-things (IoT) underpinned by ultra-low power (ULP) short-range radios that can secure long battery life or can be directly powered by energy-harvesting sources
We propose a hybrid to-digital converter (TDC) that extends the input range of a vernier-TDC with little power overhead by reusing one of its two delay chains as a flash-TDC
A design trade-off exists between the TDC range and settling time in the digitalto-time converter (DTC)-assisted all-digital phase-locked loop (ADPLL) architecture
Summary
R ECENT years have witnessed the rapid development of internet-of-things (IoT) underpinned by ultra-low power (ULP) short-range radios that can secure long battery life or can be directly powered by energy-harvesting sources. By employing a digitalto-time converter (DTC)-assisted architecture proposed in [4] in order to narrow the phase error between the reference and the DCO output clocks, the input range of the following time-to-digital converter (TDC) can be substantially reduced, drastically improving the latter’s power consumption and linearity. Since the DTC needs to generate a wide delay range covering the full oscillator period and to maintain good linearity to minimize fractional spurs, a relatively sizable power consumption is still typically required. In [6], the ADPLL using an isolated DAC-based constant-slope DTC with sub-1 ps INL achieves a worst-case fractional spur of −56 dBc and rms jitter of 0.53 ps, while consuming 980 μW, resulting in an excellent FoM of −246 dB.
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