A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS

Abstract

A 50Gb/s PAM-4 optical receiver with Silicon Photonic (Si-Ph) photodiode (PD) and CMOS linear transimpedance amplifier (TIA) is presented. To optimize both noise and bandwidth, a two-stage front-end architecture—a high gain-low bandwidth TIA followed by a two-stage continuous time linear equalizer (CTLE) is adopted. Gain adjustment of the entire link is achieved by adjusting the TIA feedback resistor and the voltage of variable gain amplifier (VGA) to ensure that the receiver analog front-end (AFE) remains linear over the entire photocurrent input range. The chip has been realized in 40nm CMOS process. Experimental results show the TIA achieves 66dBΩ transimpedance gain, 24.4GHz bandwidth, 20dB gain dynamic range, maximum overload current 2mA, and differential output swing of 400mV. The total power consumption of the chip is 125.4mW.