A 5+ 1-lane 3–10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology

Abstract

In this paper, a 3---10 Gbps source synchronous receiver macro in 65 nm CMOS technology is presented. The receiver consists of 5 data lanes and a forwarded clock lane, featuring a wide frequency operating range. In the forwarded clock lane, a duty cycle correction loop is implemented to cancel the clock duty cycle distortion. A DLL with a wide locking range from 1 to 6 GHz is designed to generate quadrature clocks. Time-averaging is used to improve clock quality. A linear equalizer with level shift and offset cancellation is implemented in the DC coupled data lane, which compensates the channel loss and shifts the data DC level to accommodate NMOS input amplifier to save power. The phase interpolator based CDR design is optimized and a ring counter based phase interpolator controller is implemented to realize the phase rotation. The power consumption for the 5+ 1 lane RX PHY core running at 10 Gbps is 175 mW or 3.5 mW/Gbps under 1.2 V power supply, achieving a BER < 1e-12.