A 4-READ 2-WRITE Multi-Port Register File Design Using Pulsed-Latches

Abstract

Pulsed-latches provide high performance with low power consumption by taking the advantages of both flip-flops and latches and thus, they are targeted in implementing different kinds of memory devices in various applications. One such memory device is the register files, which is traditionally being realized using SRAMs. In this paper, an area efficient and low power consumption design approach is proposed to perform the multi-read and multi-write operations in the pulsed-latches based multiport register files. These register files showed significant decrease in area as well as power consumption when compared to the SRAM based register files. An 8-BIT 4-READ and 2-WRITE (4R2W) pulsed-latches based multiport register file were designed and simulated in 180nm technology and its power-delay product was analyzed.