Investigation of process variation on register files in 65nm technology

Abstract

Modern on-chip memories demand a increasing need for higher performance, lower power consumption and improved robustness with shrinking feature size. The process variations are expected to be more pronounced in advanced process technology commonly used in memories such as SRAM. Variations in the critical process parameters such as threshold voltage or effective channel length can result in large number of faulty cells in a memory. These variations can result in reduced maximum attainable operating frequency, yield and circuit performance. In this paper, the impact of mismatch and process-variation on standard 6T cell is investigated. Then a register file is designed in 65nm Technology with six-transistor SRAM and investigated for the leakage power and performance under process variation. Each entry of the register file is analyzed for the performance degradation and clear, partially affected and fully affected registers are identified under process variation due to delay and leakage. Random variation alone is modeled as they are the dominant cause of process variation. It is found that the access time increases with the size of the register file and the leakage power under process variation is 22 times larger than the normal leakage power with unaffected system.