A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Abstract

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).