Abstract
In this paper, a 4.8 GHz fully integrated low power, low phase noise phase-locked loop (PLL) frequency synthesizer ready for WLAN application is presented. It is implemented in a 0.18 mum IP6M CMOS process. The chip consumes only 16 mA (including local buffers to the receiver and transmitter) from a 1.8 V supply and occupies an area of 1.85times1.1 mm2. From measurements, its in-band phase noise is -55.8 dBc/Hz and out-of-band phase noise is -119 dBc/Hz at 3 MHz offset. With the help of digital controlled capacitor array (DCCA) this frequency synthesizer can lock from 4.2 - 4.82 GHz
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