A 450-Mb/s analog front end for PRML read channels

Abstract

The high user densities and data rates supported by today's hard-disk drives (HDD) demand complex read channel ICs. High-performance analog front-end (AFE) circuits provide automatic gain control (AGC), programmable band limiting and pulse shaping prior to signal sampling and further processing of the data in the digital domain. A 450 Mb/s analog front-end, integrated into a 16/17 code rate EPR4 read channel, contains an AGC loop, which includes a programmable gain stage (PGA), an exponential variable-gain amplifier (VGA), a 7/sup th/-order 120 MHz lowpass filter (LPF), an active dc offset cancellation circuit, and digital feedback. Utilizing multilevel qualification and a variable loop time constant, the AGC acquires a 12 dB gain change within 5 data bytes. Thermal asperity (TA) and amplitude asymmetry compensation make the analog front-end ideally suited for magnetoresistive (MR) head-based applications. Implemented in 5V/3.3V dual voltage 0.35 /spl mu/ BiCMOS, the complete circuit occupies 2.29 mm/sup 3/ and dissipates 232 mW.