A 43-Gb/s Clock and Data Recovery OEIC Integrating an InP–InGaAs HPT Oscillator with an HBT Decision Circuit

Abstract

This paper presents a 43-Gb/s clock and data recovery (CDR) optoelectronic integrated circuit (OEIC) that consists of a 43-GHz heterojunction phototransistor (HPT) oscillator as an optoelectronic clock recovery circuit and a 40-Gb/s-class heterojunction bipolar transistor (HBT) decision circuit. The layer and fabrication process of the HPT and HBT are fully compatible, and the HPT has a photocoupling window in the emitter electrode for optical access from the top. When the HPT is directly illuminated, the HPT oscillator successfully extracts a 43-GHz electrical clock signal from a 43-Gb/s optical data stream by itself. The OEIC regenerates the data signal input into the HBT decision circuit by using the electrical clock signal optoelectronically extracted by the HPT oscillator. The CDR OEIC achieves error-free operation for a 2/sup 31/-1 PRBS data signal. The power dissipation of the OEIC is only 0.79 W, which is less than half that of a fully electrical 40-Gb/s-class CDR IC. This is the first successful demonstration of HPT-based OEICs integrated with HBT digital circuits operating at such a high bit rate.