A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

Abstract

Resistive random access memory (RRAM) based compute-in-memory (CIM) has shown great potentials for deep neural network (DNN) inference. Prior works generally used off-chip write-verify scheme to tighten the RRAM resistance distribution and used off-chip analog-to-digital converter (ADC) references to fine-tune partial sum quantization edges. Though off-chip techniques are viable for testing purposes, they are unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate offsets induced by process variation to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W for 1×1b MAC operations on VGG-8 network.