Abstract
Serial data communication systems operating at throughputs of 40Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAs and InP at speeds of 40Gb/s or higher [1–3]. CMOS implementations of half-rate MUX circuits have been also reported [4–5]. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40Gb/s data signals and generation of 40GHz clock signals.
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