A 4–20 GHz switched-line true time delay in GaAs pHEMT technology

Abstract

A 5-bit switched-line true time delay (TTD) circuit is proposed based on 0.25-μm GaAs pHEMT technology. The delay structure within the TTD units is formed by employing second-order all-pass networks (APNs). A double-pole double-throw (DPDT) switch is specifically designed to replace the conventional cascading of two single-pole double-throw (SPDT) switches, thus, minimizing the insertion loss introduced by the switches. To mitigate insertion loss fluctuation across different states, several π-type resistive attenuators are incorporated into the reference line. This configuration enables a maximum delay of 199.75 ps, a delay resolution of 6.45 ps, and simultaneously maintains a low delay error within 4.6 ps. The measured average insertion loss is 14.8 dB with a loss error below 3 dB, and the in/out return loss is better than −12 dB at 4–20 GHz.