A 4 × 14-Gbps/ch VCSEL array driving ASIC in 65 nm CMOS for high-energy physics experiments

Abstract

This paper presents the design and test results of a 4 × 14 Gb/s vertical cavity surface emitting laser (VCSEL) array driver VLAD14 fabricated in 65 nm CMOS technology. A novel output driving stage in VLAD14 is proposed to improve the bandwidth comparing to the conventional structure. VLAD14 outputs a 2 mA bias current and a 6 mA modulation current with a power consumption of 52 mW/ch when working at 14 Gbps/ch. The driver die has been tested with the VCSEL array load and wide-open optical eyes have been captured at 14 Gbps/ch.