A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration

Abstract

This paper presents a 7-bit 5-GS/s time-interleaved SAR ADC with background timing skew calibration. The two-step approaching skew calibration was proposed to reduce the tuning range of the digital control delay circuit, thus suppress the additional clock jitter. The ping-pong domino-SAR ADC architecture was proposed to speed up channel-ADCs. The prototype ADC consumes a total power of 38 mW from a 1.2V supply and occupies an active area of 0.69 mm2 in a 55 nm low-power CMOS technology. For 10 MHz input, the measured SNDR and SFDR are 42.7 and 65 dB, respectively. The ENOB is 6.8 bits, equivalent to the peak FOM of 69 fJ/conversion-step. At the Nyquist rate, this ADC achieves 35.9 dB SNDR and 45 dB SFDR The ENOB is 5.7 bits, equivalent to the Nyquist FOM of 150 fJ/conversion-step.