A 3.36-GHz Locking-Tuned Type-I Sampling PLL With −78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques

Abstract

This brief describes a type-I analog sampling phase-locked loop (S-PLL) featuring reference-feedthrough-suppression and narrow-pulse-shielding techniques in a single path to improve the reference (REF) spur. Specifically, we realize the former by inserting a T-shape switch with one center-tap ground, while the latter tackles the voltage ripple caused by the sampling non-idealities. Also, we can tune an external varactor to eliminate both the gain variation of the phase detector and the gate leakage of the frequency-tuning varactor. Prototyped in a 28-nm CMOS, the proposed S-PLL achieves a -78.6-dBc REF spur and 124.6-fs integrated RMS jitter. The corresponding jitter-power Figure-of- Merit is -252.8 dB.