A −254.1-dB FoM 2.4-GHz Subsampling PLL With a −76-dBc Reference Spur by Employing a Varactor-Based Cancellation Technique

Abstract

This letter presents a simple yet elegantly effective method to reduce reference spurs in analog subsampling phase locked loops (SS-PLLs) via a varactor cancellation technique. Specifically, an active-mixer-adopted phase detector is employed, whose natural (undesired) change in gate-to-drain/source capacitance during phase detection is counteracted with a carefully sized varactor diode driven directly by the (synchronous) reference signal. Implemented in 65-nm CMOS technology, seven different die measurements show the designed SS-PLL achieves a worst-case reference spur of −74 dBc and a best-case spur of −78 dBc. Drawing 1 mA from 1-V power supply, the SS-PLL achieves an integrated rms jitter of 195 fs, for a near-state-of-the-art jitter-power figure of merit of −254.1 dB, yet with a state-of-the-art reference spur.