Abstract
On the chip described, dynamic shift registers are combined with high-density serial-parallel-serial charge-coupled-device (SPS CCD) memory blocks in order to obtain a switchable chain of delay blocks with delay values that are powers of two. The shift-register length can be adjusted from 17 to 32767 clock periods. The tradeoff between the delay implementations is presented. A detailed description of the SPS CCD are given. The chip has been realized in a 2.5-/spl mu/m NMOS process with CCD option.
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