Abstract
On this chip dynamic shift registers are combined with high density CCD SPS memory blocks. The shift register length can be adjusted from 17 to 32767 clock periods. The chip has been realized in a 2.5 ?n NMCS process with CCD option.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
