A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

Abstract

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f_{in} = 1.83\,\hbox{MHz}, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio \hbox{(SNDR)} = 46.5\,\hbox{dB} at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 μm CMOS process, a high bandwidth was achieved. Since the ADC maintains an \hbox{SNDR} \ge 40\,\hbox{dB} for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.