A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc Reference Spur

Abstract

This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a transformer-based rich-harmonic shaping voltage-controlled oscillator, the proposed S-PLL at 3.78 GHz exhibits an integrated jitter of 39.6 fsRMS (1 kHz to 100 MHz), and the jitter-power figure-of-merit scores −260.2 dB. The reference (REF) spur is −70.96 dBc due to the embedded REF-feedthrough suppression technique.