A 280-KBytes Twin-Bit-Cell Embedded NOR Flash Memory With a Novel Sensing Current Protection Enhanced Technique and High-Voltage Generating Systems

Abstract

A novel sensing current protection enhanced (SCPE) technique and high-voltage (HV) generating systems are adopted to greatly enhance the advantages of the twin-bit cell. The SCPE technique provides the tradeoff of sensing margin loss between “1” and “0” bits sensing case to realize fast read access. The read speed is improved by 7.7%. HV generating systems with parallel-series-transform and capacitance-shared techniques are proposed to satisfy the complicated requirements of output capability and current drivability with lower area penalty. The HV periphery area decreases by 71%. A 1.5-V 280-KBytes embedded NOR flash memory IP has been fabricated in HHGrace (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm 4 poly 4 metal CMOS process. The complicated operation voltages and access time of 23.5 ns have been achieved at 1.5 V. The die size of the proposed IP is 0.437 mm $^{2}$ and the area size of charge pump has been reduced to 0.006 mm $^{2}$ on average.