A 26 GHz Power Amplifier with 26.4 dB Power Gain and 22.1 dBm Output Power in 65 nm CMOS

Abstract

In this paper, a 26 GHz two-stage differential CMOS power amplifier (PA) is proposed for 5G communication with 65-nm CMOS process. A differential capacitive-neutralized common source gain cell is used to maintain the stability as well as to boost the gain and output power performance. Meanwhile, to achieve good overall performance, the output and inter-stage impedances of the PA are optimized by balancing the amplifier power gain, power added efficiency (PAE) and output power. A low loss four-way transformer-based power combining network is adopted in this PA to achieve high gain and output power performance. With measurements, the PA achieves a peak gain of 26.4 dB at 26 GHz with a bandwidth from 24.7 to 28.5 GHz. At 1dB compression and saturated points, the PA delivers an output power and PAE of 18.8/22.1 dBm and 15.97/33.26%, respectively. The core chip area without pads is 0.805 mm$^{\mathbf{2}}$.