A Floating-Body Transistor-Based Power Amplifier for Sub-6-GHz 5G Applications in SOI CMOS 130-nm Process

Abstract

A floating-body transistor based two stages power amplifier (PA) with lateral NPN based bandgap voltage reference (BVR) is implemented in a 130 nm Silicon-On-Insulator (SOI) CMOS process for sub-6GHz 5G applications. Floating-body (FB) transistors instead of traditional body-contacted (BC) transistors have been adopted in driver stage and power stage amplifiers of the proposed PA. On-chip input and output transformer baluns (TB) are customized designed for this PA which can realize impedance matching. Split push-pull structure is adopted in both driver stage and power stage with inter-stage matching networks. Incorporating bonding wire multi-physics models into input and output matching and power gain temperature compensation, the proposed PA can achieve maximum 25.6 dB power gain, 22.2 dBm output power and 28% power added efficiency (PAE) at 1 dB compression point (OP-1dB). The 3 dB bandwidth of the proposed PA is from 4.3 GHz to 6.4 GHz and the core size is 0.59 mm2. When the proposed PA is used for IEEE 802.11ac application and measured at VHT80 MCS9 (80MHz, 256-QAM), it can achieve 21.4 dBm output power and 24.8% PAE at 5.5 GHz operating frequency with −36 dB error vector magnitude (EVM).