A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

Abstract

A technique is presented for implementing time-interleaved pipelined high-speed digital ΔΣ modulators using standard cells and the tools for digital design (synthesis and automatic place-and-route). Time interleaving allows clocking the standard cell blocks at submultiples of the final sampling rate. The proposed technique relies on inserting additional delays between the cascaded stages of a MASH ΔΣ modulator to reduce the complexity of the time-interleaved implementation and to eliminate any critical path spanning more than one accumulator. These additional delay stages segment the time-interleaved pipeline sections, preventing any coupling among them. The only custom designed block is a high-speed MUX used to multiplex the low-rate bit streams into the final high-rate stream. The widespread use of digital design tools considerably reduces the design time, improving the time-to-market. A prototype second-order MASH ΔΣ modulator has been fabricated in CMOS 45 nm-LP process. Operating at 2.5 GHz, it draws 6.9 mW from the nominal 1.1 V supply, while at 3.3 GHz it draws 11 mW from a 1.2 V supply.