A 250MHz-2GHz wide range delay-locked loop

Abstract

This paper describes a wide range delay-locked loop (DLL) for synchronous clocking, to support dynamic frequency and voltage scaling. The DLL achieves a wide range by using multiple phases from its variable delay line. A phase detector is proposed to increase the locking speed and alleviate the phase offset owing to the inherent mismatch of the charge pump. The DLL achieves a static phase error of under 10 ps. At 1 GHz, its RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps respectively.