Abstract
A high-speed dual-modulus divide-by-32/33 prescaler has been developed in a 0.25 /spl mu/m CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25 /spl mu/m CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6 mA at input frequency of 2.5 GHz.
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