A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC

Abstract

To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in [1] has difficulty maintaining optimal loop characteristics, which vary easily due to PVT variations or a change in the output frequency. To facilitate the calibration of loop characteristics, the FPEC can be implemented in an all-digital PLL (ADPLL), increasing the control word of a DCO, D FCW , in a very short duration, T FPEC , as shown in Fig. 25.4.1. Since the FPEC technique can rapidly remove the accumulated jitter of the DCO from the previous reference period, f REF , the variance of the output jitter, VAR[J OUT ](f), becomes saw-tooth-shaped along with the accumulating jitter. In a conventional ADPLL, the accumulated jitter is removed gradually over T REF , so the variance of the jitter is nearly constant [2]. This difference enables the FPEC ADPLL to have much lower RMS jitter, σ RMS . However, the FPEC ADPLL is limited in its ability to achieve extremely low jitter, i.e., it cannot reduce σ RMS as much as analog FPEC PLLs can. This is because typical ADPLL TDCs provides less precise information regarding the oscillator jitter than a PD does in analog PLLs. When it detects a timing error, τ err , a TDC generates a digitized value, D TDC ; thus, the amount of error to be corrected becomes rather than τ err . This results in a quantization error, τ q , thereby increasing σ rms . To minimize τ q (or E[τ q 2]), the resolution of a TDC must be improved significantly to a level at which the quantity of jitter can be distinguished, but this is difficult when a typical CMOS process is used. Even if the design itself were possible, additional power would be required to generate many evenly spaced time thresholds.