Low-Jitter Phase-Locked Loop With Ring Voltage Controlled Oscillator Using a Prompt Phase-Error Compensation Technique

Abstract

A ring-type voltage-controlled oscillator (VCO) based phase-locked loop (PLL) is presented, with low jitter. Type-I and type-II PLLs cannot provide a low-jitter performance. Injection-locked clock multipliers (ILCM) were a good solution, but they could not have a high multiplication factor because of reference spur problem, and also their jitter performance was still not preferable as they do not have integrator of a VCO. ILCMs cannot correct drifts of free running frequencies. So the prompt phase error compensation technique (PPEC) is introduced, which prototype is the phase-realignment mechanism of ILCM. Proposed design can achieve higher multiplication factor, lower jitter for frequencies different from free-running frequency, due to ring VCO. The main idea of the PPEC technique is to almost fully remove the jitter, that has been accumulated during the previous period of the clock signal, in a short period of time, thus achieving low-jitter performance. Suggested design includes switch-loop filter (SLF) and the PPEC technique realization circuit. The flaw of increase in area and power consumption will be considered.