A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology

Abstract

In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inductively degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P-1dBin) and power consumption. In low power design, above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each performance factor in low power design and optimize figure of merit (FoM) with some specification goal.