Abstract
This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.
Highlights
A wireless sensor network (WSN) develops very fast in the market because it offers great functions.The WSN has basic specifications such as the accuracy, flexibility, reliability, expenses, power consumptions and the difficulty of designing [1]
SIMULATION RESULTS In order to generate S-parameters, noise figure, stability and linearity, the simulations are carried out using the Cadence Spectre analog design environment (ADE)
A very low power 2.4 GHz two stages CMOS low noise amplifier (LNA) using forward body bias technique has been proposed in this work
Summary
A wireless sensor network (WSN) develops very fast in the market because it offers great functions.The WSN has basic specifications such as the accuracy, flexibility, reliability, expenses, power consumptions and the difficulty of designing [1]. The power consumption is the most important specification due to the battery powered of the nodes [2] This specification leads to a great development of CMOS RF usage in a research area. In [12], the topology of a two-stage cross-coupling cascaded common gate (CG) is adapted by using 0.18 μm TSMC process. It achieves gain of 16 .8 dB and power consumption of 2.16 mW. By using a current -reused topology can obtain low power consumption [13] It achieves gain of 14 dB and 2.45 mW. The proposed design uses a few inductors a nd increa ses the chip size
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