Abstract
A 30-Gb/s differential limiting amplifier (LA) composed of three cascaded stages is presented. Fabricated in 65-nm CMOS process, the proposed LA yields a typical gain of 31.1 dB and a -3-dB bandwidth of 22.1 GHz while consuming 23 mW from a 1-V supply. The measured gain tuning range is 10 dB with the maximum gain step size less than 1 dB. DC offset cancellation is implemented by a feedback loop consisting of a low-pass filter (LPF) and an amplifier. Optical measurements demonstrate that the degradation in RMS jitter for a 25-Gb/s PRBS due to supply variation from 1 V to 0.9 V can be improved from 37% to 22% using the LA's digital programmability. At 80°C, the RMS jitter can be improved by 16% with the optimal digital control. The core chip area is about 0.12 mm 2 .
Published Version
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