A 230–260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_{{\mathrm{max}}}$ -Core

Abstract

This paper proposes a wideband and high-gain amplifier design technique based on a dual-peak maximum achievable gain ( $G_{\mathrm{ max}}$ ) core. The proposed technique achieves a power gain close to $G_{\mathrm{ max}}$ at two frequencies simultaneously, thereby enabling the implementation of a wideband and high-gain amplifier. The input, output, and interstage matching networks are designed in a gain compensating manner, considering the gain variation of the dual-peak $G_{\mathrm{ max}}$ -core. The four-stage amplifier based on an identical dual-peak $G_{\mathrm{ max}}$ -core at each stage is implemented in a 65-nm CMOS process. The measured results show a 3-dB bandwidth of 30 GHz (227.5–257.2 GHz), a gain of 12.4 ± 1.5 dB, and a peak power added efficiency (PAE) of 1.6% with dc power dissipation of 23.8 mW, which corresponds to the widest 3-dB bandwidth and gain per stage comparable to those of other reported CMOS amplifiers operating at frequencies above 200 GHz.